ISA 总线定义

Interrupt Request 5

B24

IRQ4

Interrupt Request 4

B25

IRQ3

Interrupt Request 3

B26

/DACK2

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DMA Acknowledge 2

B27

T/C

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Terminal count; pulses high when DMA term. count reached

B28

ALE

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Address Latch Enable

B29

+5V

　

+5 VDC

B30

OSC

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High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)

B31

GND

　

Ground

　

　

　

　

C1

SBHE

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System bus high enable (data available on SD8-15)

C2

LA23

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Address bit 23

C3

LA22

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Address bit 22

C4

LA21

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Address bit 21

C5

LA20

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Address bit 20

C6

LA18

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Address bit 19

C7

LA17

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Address bit 18

C8

LA16

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Address bit 17

C9

/MEMR

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Memory Read (Active on all memory read cycles)

C10

/MEMW

" src="mhtml:http://www.pp51.com/za/300/data/ISA .mht!http://www.hj-tech.com/file/sup/io/pcisa/gif/arrowlr.gif" width=32 border=0>

Memory Write (Active on all memory write cycles)

C11

SD08

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Data bit 8

C12

SD09

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Data bit 9

C13

SD10

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Data bit 10

C14

SD11

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Data bit 11

C15

SD12

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Data bit 12

C16

SD13

" src="mhtml:http://www.pp51.com/za/300/data/ISA .mht!http://www.hj-tech.com/file/sup/io/pcisa/gif/arrowlr.gif" width=32 border=0>

Data bit 13

C17

SD14

" src="mhtml:http://www.pp51.com/za/300/data/ISA .mht!http://www.hj-tech.com/file/sup/io/pcisa/gif/arrowlr.gif" width=32 border=0>

Data bit 14

C18

SD15

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Data bit 15

D1

/MEMCS16

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