摘要：DS26502的数据资料包含了在各类应用中使用DS26502所需的所有信息。数据资料是为使用软件模式的用户而写的，提供了通过控制寄存器配置DS26502所需的信息，但并没有包含在硬件模式下如何配置DS26502的内容。
本应用笔记着重讨论在硬件模式下使用DS26502的方法，不再赘述数据资料中已涵盖的，只与软件模式相关的内容。
简介
DS26502有两种主要的操作模式：软件模式和硬件模式。这里的“模式”是指器件的控制方式。采用软件模式的应用利用微控制器的串行或并行总线与DS26502内部的控制寄存器通信，达到控制其工作的目的。在硬件模式中，串行/并行通信接口引脚被重新分配了新的功能，以便能够通过这些引脚的逻辑状态直接控制DS26502的内部工作。
什么时候应该用硬件模式？
在硬件模式下使用DS26502的优点是无需用微控制器来控制其工作。
硬件模式是否可用取决于具体应用的特殊要求。设计者需要重点考虑的是，确定目标应用是否会用到一些只能在软件模式下使用的功能。表1列出了所有只能在软件模式下使用，硬件模式下不可用的功能。并给出了寄存器位及其名称，以便于参照DS26502数据资料中的完整功能描述。
硬件模式的实现
硬件模式下DS26502的工作受控于外部引脚。表2列出了软件模式中的一些控制位和与之相对应的、用于在硬件模式下控制DS26502的引脚的作用。
除了一些软件可控的功能在硬件模式下完全丧失外，还有一些功能仍然存在，但不可更改。这些不可更改的功能如表3所示，是按照使用硬件模式的常规应用的要求精挑细选的。硬件模式下每个引脚功能的完整描述在表4中给出。图1到图4是DS26502硬件模式下的功能框图。这些框图与数据资料中所给出的软件模式下的情况相似。不同的是，软件模式中对应于控制寄存器的位置在这里被替换为DS26502的外部引脚。软件模式特有的功能也被去掉了。
尽管大多数DS26502应用采用的是软件模式，硬件模式对于许多用户而言仍然是一个可用的选项。本应用笔记再加上DS26502数据资料所提供的信息，有助于设计者花费最少的时间和精力，构建并实施一个硬件模式的应用。
表1. 硬件模式中无法使用的软件模式功能 RegisterDeSCRJPTionTSTRREGTest Reset RegisterIDRDevice Identification RegisterINFO1Information Register 1INFO2Information Register 2IIRInterrupt Information RegisterSR1Status Register 1IMR1Interrupt Mask Register 1SR2.7Receive Yellow Alarm Clear EventSR2.6Receive Alarm Indication Signal Clear EventSR2.5Receive Loss Of Signal Clear EventSR2.4Receive Loss of Frame Clear EventSR2.3Receive Yellow Alarm ConditionIMR2Interrupt Mask Register 2SR3Status Register 3IMR3Interrupt Mask Register 3SR4Status Register 4IMR4Interrupt Mask Register 4INFO3Information Register 3RAFReceive Align Frame RegisterRNAFReceive Non-Align Frame RegisterRSiAFReceive Si Bits of the Align FrameRSiNAFReceive Si Bits of the Non-Align FrameRRAReceive Remote AlarmRSa4Receive Sa4 BitsRSa5Receive Sa5 BitsRSa6Receive Sa6 BitsRSa7Receive Sa7 BitsRSa8Receive Sa8 BitsTEST1-16Test Register 1-16
表2. 硬件模式下的控制引脚与寄存器的对应关系 POSTTTIONPinNameIOCR1.5RSMRS_8K Mode SelectIOCR1.2TSMTS_8K_4 Mode SelectT1RCR2.5HBEReceive B8ZS EnableT1TCR2.7HBETransmit B8ZS EnableMCREG.7TMODE3Transmit Mode Configuration 3MCREG.6TMODE2Transmit Mode Configuration 2MCREG.5TMODE1Transmit Mode Configuration 1MCREG.4TMODE0Transmit Mode Configuration 0MCREG.3RMODE3Receive Mode Configuration 3MCREG.2RMODE2Receive Mode Configuration 2MCREG.1RMODE1Receive Mode Configuration 1MCREG.0RMODE0Receive Mode Configuration 0TPCR.1TCSS1Transmit Clock (TX CLOCK) Source Select 1TPCR.0TCSS0Transmit Clock (TX CLOCK) Source Select 0SR2.2RAISReceive Alarm Indication SignalSR2.1RLOSReceive Loss Of Signal ConditionSR2.0RLOF_CCEReceive Loss of Frame ConditionE1RCR.5HBEReceive HDB3 EnableE1TCR.1HBETransmit HDB3 EnableLBCR.2RLBRemote loopback enabledLIC1.7L2Line Build-Out Select 2LIC1.6L1Line Build-Out Select 1LIC1.5L0Line Build-Out Select 0LIC2.4TAISTransmit Alarm Indication SignalLIC2.3JACKSJitter Attenuator MuxLIC4.7MPS1MCLK Prescaler 1LIC4.6MPS0MCLK Prescaler 0
表3. 硬件模式默认功能 POSTTTION NameHardware Mode FunctionIOCR1.6RS_8K Mode Select 2T1 Mode: (when RMS = 0)do not pulse double-wide in signaling framesE1 Mode: (when RMS = 1)RS_8K outputs CAS multTFRAME boundariesIOCR1.4RLOF_CCE Output Functionreceive loss of frame (RLOF)IOCR1.3Composite Clock Sync Mode_ Transmit Signaling Double-Wide Sync(CC64K) 8kHz reference, (T1) normal sync pulsesIOCR1.1TS_8K_4 I/O SelectTS_8K_4 is an inputIOCR1.0Output Data Formatbipolar data at TPOS and TNEGIOCR2.7RCLKInvert no inversionIOCR2.6TCLKInvert no inversionIOCR2.5RS_8K Invertno inversionIOCR2.4TS_8K_4Invert no inversionT1RCR1.6Auto Resync Criteriaresync on OOF or RLOS eventT1RCR1.5T1RCR1.4Out Of Frame Select BitsOut Of Frame Criteria2/4 frame bits in errorT1RCR1.3Sync CriteriaIn D4 Framing Mode:search for Ft pattern, then search for Fs patternIn ESF Framing Mode:search for FPS pattern onlyT1RCR1.2Sync Timequalify 10 bitsT1RCR1.1Sync Enableauto resync enabledT1RCR1.0ResynchronizeNo manual resynchronization of the receive side framer allowedT1RCR2.1Receive Japanese CRC6 Enableuse ANSI/AT&T/ITU CRC6 calculation (normal operation)Japanese CRC6 not availableT1RCR2.0Receive Side D4 Yellow Alarm Selectzeros in bit 2 of all channelsT1TCR1.7Transmit Japanese CRC6 Enableuse ANSI/AT&T/ITU CRC6 calculation (normal operation)Japanese CRC6 not availableT1TCR1.6Transmit F-Bit Pass-ThroughF bits sourced internallyT1TCR1.5Transmit CRC Pass-Throughsource CRC6 bits internallyT1TCR1.0Transmit Yellow Alarmcannot transmit yellow alarmT1TCR2.6Transmit Fs-Bit Insertion EnableFs-bit insertion enabledT1TCR2.4Bit 4/F-Bit Corruption Type 2No bit corruption supportT1TCR2.3F-Bit Corruption Type 1No bit corruption supportT1TCR2.2Transmit-Side D4 Yellow Alarm Select0s in bit 2 of all channelsT1TCR2.0Transmit-Side Bit 7 Zero-Suppression Enableno stuffing occursT1CCR.4Transmit RAI-CI Enabledo not transmit the ESF RAI-CI codeT1CCR.3Transmit AIS-CI Enabledo not transmit the AIS-CI codeT1CCR.1Pulse-Density Enforcer Enabledisable transmit pulse-density enforcerTPCR.7Transmit PLL Output Frequency Select 1in hardware mode, use TMODE pinsTPCR.6Transmit PLL Output Frequency Select 0in hardware mode, use TMODE pinsTPCR.5PLL_OUT SelectPLL_OUT is sourced directly from the TX PLLTPCR.4Transmit PLL Input Frequency Select 0in hardware mode, use RMODE pinsTPCR.3Transmit PLL Input Frequency Select 1in hardware mode, use RMODE pinsTPCR.2Transmit PLL_CLK Source SelectUse the recovered network clock. This is the same clock available at the RCLK pin (output)E1RCR.6Receive Loss Of SignalRLOS declared upon 255 consecutive zeros (125µs)E1RCR.2Frame Resync Criteriaresync if FAS received in error three consecutive timesE1RCR.1Sync Enableauto resync enabledE1RCR.0ResyncNo manual resyncE1TCR.7Transmit Time Slot 0 Pass-ThroughFAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF registersE1TCR.4Transmit International Bit Selectsample Si bits at TSER pinBOCC.4Receive BOC Enablereceive BOC function disabledBOCC.3Receive BOC ResetNo manual reset of the BOC circuitryBOCC.2Receive BOC Filter Bit 1sets the number of consecutive patterns that must be received without error prior to an indication of a valid messageBOCC.1Receive BOC Filter Bit 0sets the number of consecutive patterns that must be received without error prior to an indication of a valid messageBOCC.0Send BOCDo not transmit BOC codeLBCR.3Local LoopbackLocal loopback disabledLIC1.4Receive Equalizer Gain LimitT1 Mode: -36dB (long haul)E1 Mode: -43dB (long haul)LIC1.3Jitter Attenuator Selectplace the jitter attenuator on the receive sideLIC1.2Jitter Attenuator Buffer Depth Select128 bitsLIC1.1Disable Jitter Attenuatorjitter attenuator enabledLIC1.0Transmit Power-Down normaltransmitter operationLIC2.6Line Interface ResetNo manual reset supportedLIC2.5Insert BPVNo insert BPV supportedLIC2.2Receive Composite Clock Filter EnableReceive Composite Clock Filter DisabledLIC2.1Short Circuit Limit Disable (in E1 mode)enable 50mA current limiterLIC2.0Custom Line Driver Selectnormal operationLIC3.7CMI Enabledisable CMI modeLIC3.6CMI InvertCMI normal at TTIP and RTIPLIC3.4Monitor Mode 1Normal operation (no boost)LIC3.3Monitor Mode 0Normal operation (no boost)LIC3.0Transmit Alternate Ones and ZerosdisabledTLBC.6Automatic Gain Control Enableuse Transmit AGC, TLBC bits 0-5 are "don't care"TLBC.5Gain Control BitNot usedTLBC.4Gain Control BitNot usedTLBC.3Gain Control BitNot usedTLBC.2Gain Control BitNot usedTLBC.1Gain Control BitNot usedTLBC.0Gain Control BitNot usedTAF.7International Bit0TAF.6Frame Alignment Signal Bit (0)0TAF.5Frame Alignment Signal Bit (0)0TAF.4Frame Alignment Signal Bit (1)1TAF.3Frame Alignment Signal Bit (1)1TAF.2Frame Alignment Signal Bit (0)0TAF.1Frame Alignment Signal Bit (1)1TAF.0Frame Alignment Signal Bit (1)1TNAF.7International Bit (Si)0TNAF.6Frame Nonalignment Signal Bit (1)1TNAF.5Remote Alarm (used to transmit the alarm A)0TNAF.4Additional Bit 4 (Sa4)0TNAF.3Additional Bit 5 (Sa5)0TNAF.2Additional Bit 6 (Sa6)0TNAF.1Additional Bit 7 (Sa7)0TNAF.0Additional Bit 8 (Sa8)0TSiAF.0-7Si Bit of Frames 0, 2, 4, 6, 8, 10, 12, 140 in all bit LOCAIIONsTSiNAF.0-7Si Bit of Frames 1, 3, 5, 7, 9, 11, 13, 150 in all bit LOCAIIONsTRA.0-7Remote Alarm Bit of Frame 1, 3, 5, 7, 9, 11, 13, 150 in all bit LOCAIIONsTSa4.0-7Sa4 Bit of Frames 1, 3, 5, 7, 9, 11, 13, 150 in all bit LOCAIIONsTSa5.0-7Sa5 Bit of Frames 1, 3, 5, 7, 9, 11, 13, 150 in all bit LOCAIIONsTSa6.0-7Sa6 Bit of Frames 1, 3, 5, 7, 9, 11, 13, 150 in all bit LOCAIIONsTsa7.0-7Sa7 Bit of Frames 1, 3, 5, 7, 9, 11, 13, 150 in all bit LOCAIIONsTsa8.0-7Sa8 Bit of Frames 1, 3, 5, 7, 9, 11, 13, 150 in all bit LOCAIIONsTSACR.0-7Insertion Control Bits for TsiAF, TSiNAF, TRA, TSa4, TSa5, TSa6, TSa7, TSa8do not insert data from the registers TsiAF, TSiNAF, TRA, TSa4, TSa5, TSa6, TSa7, TSa8 into the transmit data streamRFDL.0-5BOC Bit 0-50 in all bit LOCAIIONsTFDL.7Transmit FDL Bit 7 MSB of the transmit FDL code0TFDL.6Transmit FDL Bit 60TFDL.5Transmit FDL Bit 50TFDL.4Transmit FDL Bit 41TFDL.3Transmit FDL Bit 31TFDL.2Transmit FDL Bit 21TFDL.1Transmit FDL Bit 10TFDL.0Transmit FDL Bit 0 LSB of the transmit FDL code0RFDLM1.0-7Receive FDL Match Bit 0-70 in all bit LOCAIIONsRFDLM2.0-7Receive FDL Match Bit 0-70 in all bit LOCAIIONs
[1] [2] [3] 下一页
本文关键字：硬件 电力配电知识，电工技术 - 电力配电知识
