E1线路补偿 L2
PIN 13L1
PIN 12L0
PIN 11ApplicationN (1)Return LossRt (1)00075Ω normal1:2N.M. (2)0001120Ω normal1:2N.M. (2)010075Ω with high return loss (1)1:221dB6.2Ω101120Ω with high return loss (1)1:221dB11.6Ω110Reserved———111Reserved———
T1线路补偿 L2
PIN 13L1
PIN 12L0
PIN 11ApplicationN (1)Return LossRt (1)000DSX-1 (0 to 133 feet)/0dB CSU1:2N.M.0001DSX-1 (133 to 266 feet)1:2N.M.0010DSX-1 (266 to 399 feet)1:2N.M.0011DSX-1 (399 to 533 feet)1:2N.M.0100DSX-1 (533 to 655 feet)1:2N.M.0101Reserved———110Reserved———111Reserved———注1：该模式下TTD引脚必须接高电平。
注2：N.M. = 无意义
JTAG PinNameTypeFunction34JTCLKIJTAG Clock. This clock input is typically a low-frequency (less than 10MHz), 50% duty-cycle clock signal.33JTMSIJTAG Mode Select (with Pullup). This input signal is used to control the JTAG controller state machine and is sampled on the rising edge of JTCLK.36JTDIIJTAG Data Input (with Pullup). This input signal is used to input data into the register that is enabled by the JTAG controller state machine and is sampled on the rising edge of JTCLK.37JTDOOJTAG Data Output. This output signal is the output of an internal scan-shift register enabled by the JTAG controller state machine, and is updated on the falling edge of JTCLK. The pin is in the high-impedance mode when a register is not selected or when the JTRST signal is high. The pin goes into and exits the high impedance mode after the falling edge of JTCLK35JTRSTIJTAG Reset (Active Low). This input forces the JTAG controller logic into the reset state and forces the JTDO pin into high impedance when low. This pin should be low while power is applied and set high after the power is stable. The pin can be driven high or low for normal operation, but must be high for JTAG operation.
线路接口 PinNameTypeFunction44MCLKIMaster Clock Input. A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS26502 in T1-only operation, a 1.544MHz (50ppm) clock source can be used.41RTIPIReceive Tip. Analog input for clock recovery circuitry. This pin connects through a 1:1 transformer to the network. See the Line Interface Unit section of the DS26502 data sheet for details.42RRINGIReceive Ring. Analog input for clock recovery circuitry. This pin connects through a 1:1 transformer to the network. See the Line Interface Unit section of the DS26502 data sheet for details.51TTIPOTransmit Tip. Analog line-driver output. This pin connects through a 1:2 step-up transformer to the network. See the Line Interface Unit section of the DS26502 data sheet for details.54TRINGOTransmit Ring. Analog line-driver output. This pin connects through a 1:2 step-up transformer to the network. See the Line Interface Unit section of the DS26502 data sheet for details.50THZEITransmit High-Impedance Enable. When high, TTIP and TRING will be placed into a high-impedance state.
电源 PinNameTypeFunction7,24,58DVDD—Digital Positive Supply. 3.3V, ±5%. Should be tied to the RVDD and TVDD pins.38RVDD—Receive Analog Positive Supply. 3.3V, ±5%. Should be tied to the DVDD and TVDD pins.53TVDD—Transmit Analog Positive Supply. 3.3V, ±5%. Should be tied to the DVDD and RVDD pins.8,22,56DVSS—Digital Signal Ground. 0.0V. Should be tied to the RVSS and TVSS pins.40,43,45RVSS—Receive Analog Signal Ground. 0.0V. Should be tied to the DVSS and TVSS pins.52TVSS—Transmit Analog Signal Ground. 0.0V. Should be tied to the DVSS and RVSS pins.
框图
以下图1到图4中的方框图用以说明DS26502在硬件模式下的工作原理。
这些图并未涉及所有DS26502的硬件模式引脚，只给出了那些需要在硬件模式下控制DS26502功能的引脚。本应用笔记的“引脚功能描述”部分给出了完整的引脚功能描述。以下引脚在框图中没有出现：RSM, TSM, TITD, RITD, E1TS, TAIS, L0, L1, L2, JACKS, HBE。
图1. DS26502硬件模式框图
图2. 环回复用器框图
图3. 发送PLL时钟复用器框图
图4. 主时钟PLL框图
上一页 [1] [2] [3]
本文关键字：硬件 电力配电知识，电工技术 - 电力配电知识
