发送PLL在硬件控制模式下，连接到发送PLL输入的始终是TCLK引脚。发送时钟由TCSS0和TCSS1引脚选择。PLL_OUT引脚上的信号始终和选定的发送时钟相同。如果用户想使发送器工作于恢复出来的时钟，可在外部将RCLK引脚连接到TCLK引脚。
表4. 硬件模式下的引脚功能描述 PinNameTypeFunction47PLL_OUTOTransmit PLL Output. 1544kHz, 2048kHz, 64kHz, or 6312kHz output from the internal TX PLL17TCLKITransmit Clock Input. A 64kHz, 1.544MHz, 2.048MHz, or 6312kHz primary clock. By using TCSS0 and TCSS1 pins, may be selected by the TX PLL mux to provide a clock to the transmit section6331TCSS0
TCSS1ITransmit Clock Source Select 0 and 1
Selects the output of the TX PLL Clock Mux function.
TCSS1TCSS0Transmit Clock (TX Clock) Source00The TCLK pin is the source of transmit clock01The PLL_CLK is the source of transmit clock10The scaled signal at MCLK as the transmit clock11The signal present at RCLK is the transmit clock
发送侧 PinNameTypeFunction21TSERITransmit Serial Data. Source of transmit data sampled on the falling edge of the selected transmit clock. In normal operation the selected transmit clock is output at the TCLKO pin.23TS_8K_4ITSYNC, 8kHz Sync, 400Hz Sync (400Hz Sync N/A in HW mode.)T1/E1 Mode: A pulse at this pin will establish either frame or multTFRAME boundaries for the transmit side. 64KCC Mode: Establishes the boundary for the 8kHz portion of the composite clock.18TCLKOOTransmit Clock Output. In normal operation this output is the selected transmit clock from the TX_PLL, TCLK pin, or the recovered clock (RCLK). When remote loopback is enabled this pin will output the recovered network clock.20TPOSOOTransmit Positive-Data Output. In T1 or E1 mode, updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. In 64KCC or 6312 mode, this pin will be low.19TNEGOOTransmit Negative-Data Output. In T1 or E1 mode, updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. In 64KCC or 6312 mode, this pin will be low.
接收侧 PinNameTypeFunction25RCLKOReceive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), 6312kHz (G.703 Synchronization Interface), or 64kHz (composite clock) clock.26RS_8KOReceive Sync/ 8kHZ Clock. T1/E1 Mode: An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (RSM pin = 0) or multTFRAME (RSM pin = 1) boundaries. 64KCC Mode: This pin will output the extracted 8kHz portion of the composite clock signal. 6312K Mode: This pin will be in a high-impedance state.27400HZO400HZ Clock OutputT1/E1 Mode: This pin will be in a high-impedance state.64KCC Mode: This pin will output the 400Hz clock if enabled.6312K Mode: This pin will be in a high-impedance state.28RSEROReceive Serial DataT1/E1 Mode: This is the received NRZ serial data updated on rising edges of RCLK. 64KCC Mode: This pin will be in a high-impedance state.6312K Mode: This pin will be in a high-impedance state.30RLOF_CCEOReceive Loss of Frame or Composite Clock Error T1/E1 Mode: Set when the receive synchronizer is searching for frame alignment (RLOF mode). 64KCC Mode: Active high when errors are detected in the 8kHz clock or 400Hz clock6312K Mode: This pin will be in a high-impedance state.32RLOSOReceive Loss of SignalT1 Mode: High when 192 consecutive zeros detected.E1 Mode: High when 255 consecutive zeros detected.64KCC Mode: High when consecutive zeros detected for 130ms typically.6312K Mode: High when consecutive zeros detected for 65ms typically.29RAISOReceive Alarm Indication SignalT1 Mode: Will toggle high when receive Blue Alarm is detected.E1 Mode: Will toggle high when receive AIS is detected.64KCC Mode: This pin will be in a high-impedance state.6312K Mode: This pin will be in a high-impedance state.
控制器接口 PinNameTypeFunction46JACKSIJA Clock Source SelectJA Clock Select. Set this pin high for T1 mode operation when either a 2.048MHz, 4.096MHz, 8.192MHz or 16.382MHz signal is applied at MCLK.14
49
48
62TMODE0
TMODE1
TMODE2
TMODE3ITransmit Mode Select 0, 1, 2, 3. Used to configure the transmit-operating mode. See Transmit Path Operating Mode below:
发送通道工作模式 Tmode3
Pin 62Tmode2
Pin 48Tmode1
Pin 49Tmode0
Pin 14Transmit-Path Operating Mode0000T1 D40001T1 ESF0010J1 D40011J1 ESF0100E1 FAS0100E1 FAS + CAS (Note 1)0101Reserved0110E1 CRC40110E1 CRC4 + CAS (Note 1)0111Reserved1000E1 G.703 2048kHz Synchronization Interface100164kHz + 8kHz Synchronization Interface101064kHz + 8kHz + 400Hz Synchronization Interface10116312kHz Synchronization Interface1100Reserved1101Reserved1110Reserved1111Reserved注1：DS26502内部没有产生CAS信令和复帧同步码的资源。必须将CAS信令和复帧同步码嵌入到TSER引脚上的发送数据中(TS16时隙)，帧与TS_8K_4引脚上的同步信号相对齐。
PinNameTypeFunction39TSTRSTITri-State Control and Device Reset. TSTRST high tri-states all output and I/O pins. Set low for normal operation. Useful for in-board level testing.57
59BIS0
BIS1IBus Interface Mode Select 1, 0. These bits select the controller interface mode of operation.
BIS0 = 1 and BIS1 = 1 selects Hardware Mode6RITDIReceive Internal Termination DisableThe internal receive termination value is dependent on the state of the RMODEx pins.
0 = Enable the internal receive termination.
1 = Disable the internal receive termination.5TITDITransmit Internal Termination DisableThe internal transmit termination value is dependent on the state of the TMODEx pins.
0 = Enable the internal transmit termination.
1 = Disable the internal transmit termination.34
61
64RMODE0
RMODE1
RMODE2
RMODE3IReceive Mode Select 0, 1, 2, 3. Used to configure the receiver-operating mode. See Receive Path Operating Mode below:
接收通道工作模式 Rmode3
Pin 64Rmode2
Pin 61Rmode1
Pin 4Rmode0
Pin 3Receive Path Operating Mode0000T1 D40001T1 ESF0010J1 D40011J1 ESF0100E1 FAS0101E1 CAS0110E1 CRC40111E1 CAS and CRC41000E1 G.703 2048kHz Synchronization Interface100164kHz + 8kHz Synchronization Interface101064kHz + 8kHz + 400Hz Synchronization Interface10116312kHz Synchronization Interface1100Reserved1101Reserved1110Reserved1111Reserved
PinNameTypeFunction2TSMITS_8K_4 Mode Select
In T1 or E1 operation, selects frame or multTFRAME mode for the TS_8K_4 pin.
0 = Frame Mode.
1 = MultTFRAME Mode.1RSMIRS_8K Mode Select
Selects frame or multTFRAME pulse at RS_8K pin.
0 = Frame Mode.
1 = MultTFRAME Mode.15
16MPS0
MPS1IMCLK Prescaler Select 0 and 1
Sets the prescale value for the PLL.
T1 Mode
MCLK (MHz)MPS1MPS0JACKS1.5440003.0880106.17610012.3521102.0480014.0960118.19210116.384111E1 Mode MCLK (MHz)MPS1MPS0JACKS2.0480004.0960108.19210016.38411010TAISITransmit AIS
In T1/E1 operating modes, the transmitter will transmit an AIS pattern when high. This pin is ignored in all other operating modes.
0 = Normal Transmission.
1 = Transmit AIS Alarm.9E1TSIE1 Termination Select
Selects the E1 internal termination value at both the transmitter and receiver. This pin is ignored in all other operating modes.
0 = 120Ω termination
1 = 75Ω termination55HBEITransmit and Receive B8ZS/HDB3 Enable
Enables transmit and receive B8ZS/HDB3 when in T1/E1 operating modes.
0 = HDB3/B8ZS disabled
1 = HDB3/B8ZS enabled60RLBIRemote Loopback Enable
In this loopback, data received at RTIP and RRING will be looped back to the transmit LIU. Received data will continue to pass through the receive-side framer of the DS26502 as it would normally, and the data from the transmit side formatter will be ignored. This function is only valid when the transmit side and receive side are in the same operating mode.
0 = Remote Loopback disabled
1 = Remote Loopback enabled11
12
13L0
L1
L2ILine Build-Out Select 0, 1, 2. Selects the line build-out value.For E1 see E1 Line Build-Out below: For T1 see T1 Line Build Out below:
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