VHLD实例三态总线

LIBRARY IEEE;
    USE ieee.std_logIC_1164.ALL;

ENTITY prebus IS
    PORT(
        my_in  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        sel    : IN STD_LOGIC;
        my_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END prebus;

ARCHITECTURE cpld OF prebus IS
BEGIN
    my_out <= "ZZZZZZZZ"
    WHEN (sel = '1')
    ELSE my_in;
END cpld;

本文关键字：暂无联系方式DSP/FPGA技术，单片机-工控设备 - DSP/FPGA技术