VHLD实例8位相等比较器

library IEEE;
use IEEE.Std_logIC_1164.all;
entity HCT688 is 
   port(Q, P : in std_logic_vector(7 downto 0);
         GBAR : in std_logic; PEQ : out std_logic);
end HCT688;

architecture VER1 of HCT688 is
begin
   PEQ <= '0' when ((To_X01(P) = To_X01(Q)) and (GBAR = '0')) else '1';
end VER1;

本文关键字：暂无联系方式DSP/FPGA技术，单片机-工控设备 - DSP/FPGA技术