FPGA学习Verilog HDL实验－－-小项目1

0:romout = 0;

1:romout = 1;

2:romout = 4;

3:romout = 9;

4:romout = 16;

5:romout = 25;

6:romout = 36;

7:romout = 49;

8:romout = 64;

9:romout = 81;

10:romout = 100;

11:romout = 121;

12:romout = 144;

13: romout = 169;

14: romout = 196;

15: romout = 225;

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本文关键字：小项目  DSP/FPGA技术，单片机-工控设备 - DSP/FPGA技术