FPGA学习Verilog HDL实验－－-小项目1

adda3'd0

minus3'd1

band3'd2

bor3'd3

bnot3'd4

alu(out, opcode, a, b);

[7:0] out;

[7:0] out;

[2:0] opcode;

[7:0] a,b;

@(opcodeab)

(opcode)

`adda:out = a+b;

`minus:out = a-b;

`band:out = a&b;

`bor:out = a|b;

`bnot:out = ~a;

out = 8'hx;

module

[7:0] qout;

cout;

[7:0] data;

load, cin, clk, reset;

[7:0] qout;

@(clk)

(reset)

qout <= 0;

(load)

qout <= data;

(cin)

(qout[3:0] == 9)

qout[3:0] <= 0;

(qout[7:4] == 5)

qout[7:4] <= 0;

qout[7:4] <= qout[7:4] + 1;

qout[3:0] <= qout[3:0] + 1;

cout = ((qout == 8'h59) & cin)?1:0;//

module

4'd0:decodeout = 7'b1111_110;

4'd1:decodeout = 7'b0110_000;

4'd2:decodeout = 7'b1101_101;

4'd3:decodeout = 7'b1111_001;

4'd4:decodeout = 7'b0110_011;

4'd5:decodeout = 7'b1011_011;

4'd6:decodeout = 7'b1011_111;

4'd7:decodeout = 7'b1110_000;

4'd8:decodeout = 7'b1111_111;

4'd9:decodeout = 7'b1111_011;

decodeout = 7'bx;

sum = 0;

sum = sum + 1;

pass = 1;

pass = 0;

[1] [2]  下一页

本文关键字：小项目  DSP/FPGA技术，单片机-工控设备 - DSP/FPGA技术