PIC16F84 单片机 做的频率计
;*************************************************************************
;
; Original header file for PIC 16F84 & AKIZUKI’s assembler.
; Copyright (c) 1998 by 32 Technical Laboratory (JG6DFK/QRP).
; All rights reserved.
;
;*************************************************************************
.16f84
;-------------------------------------------------------------------------
; Register definitions of bank 0.
;-------------------------------------------------------------------------
indf equ 00h ; Data I/O port for indirect addressing.
tmr0 equ 01h ; 8bits real-time cLOCk/counter.
pcl equ 02h ; Low order 8bits of the program counter. (PC)
status equ 03h ; Status register.
fsr equ 04h ; Indirect data memory address pointer 0.
porta equ 05h ; I/O ports A. (= RA0 to RA4)
portb equ 06h ; I/O ports B. (= RB0 to RB7)
ra equ 05h ; Same as PORTA.
rb equ 06h ; Same as PORTB.
eEDAta equ 08h ; EEPROM data register.
eeadr equ 09h ; EEPROM address register.
pclath equ 0Ah ; Write buffer for upper 5 bits of the PC.
iNTCon equ 0Bh ; Interrupt control register.
;-------------------------------------------------------------------------
; Register definitions of bank 1.
;-------------------------------------------------------------------------
option equ 01h ; (= 81h) Option register.
trISA equ 05h ; (= 85h) I/O ports A data direction register.
trisb equ 06h ; (= 86h) I/O ports B data direction register.
eecon1 equ 08h ; (= 88h) EEPROM data memory R/W status register.
eecon2 equ 09h ; (= 89h) I/O port for EEPROM data memory.
;-------------------------------------------------------------------------
; Others.
;-------------------------------------------------------------------------
; ----- For status register.
irp equ 7 ; Register bank select bit for indirect addressing.
rp1 equ 6 ; RP1:RP0 00 = Bank 0, 01 = Bank 1.
rp0 equ 5 ; 10 = Bank 2, 03 = Bank 3.
to equ 4 ; Time-out bit.
pd equ 3 ; Power-down bit.
z equ 2 ; Zero bit.
dc equ 1 ; Digit carry or bollow bit.
c equ 0 ; Carry or borrow bit.
; ----- For interrupt control register.
gie equ 7 ; Global interrupt enable bit.
eeie equ 6 ; EEPROM write complete interrupt enable bit.
t0ie equ 5 ; TMR0 overflow interrupt enable bit.
inte equ 4 ; RB0/INT interrupt enable bit.
rbie equ 3 ; RB port change interrupt enable bit.
t0if equ 2 ; TMR0 overflow interrupt flag bit.
intf equ 1 ; RB0/INT interrupt flag bit.
rbif equ 0 ; RB port change interrupt flag bit.
; ----- For option register.
rbpu equ 7 ; I/O ports B pull-up disable bit.
intedg equ 6 ; Interrupt edge select bit.
t0cs equ 5 ; TMR0 clock source select bit.
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