Freescale 公司的MPC8349-mITX数字家庭參考设计平台采用MPC8349E PowerQUICC II™ Pro系列统信处理器，它采用片上系统（SoC）架构，集成了增强e300核和先进的特性如DDR存储器，双吉比特以太网，双PCI和高速USB控制器。时钟速率可高达667 MHz，是最高性能的PowerQUICC II器件。MPC8349E可广泛应用在以太网路由器和交换器，无线LAN (WLAN)设备，网络存储，家庭网络，工业控制以及复印机，打印机和其它图像设备。本文介绍了MPC8349E的主要性能和方框图以及MPC8349-mITX数字家庭參考设计平台的主要性能和方框图。
The MPC8349E PowerQUICC II™ Pro family of integrated communications processors is a next-generation extension of the popular PowerQUICC II line. Based on a system-on-chip (SoC) architecture, the MPC8349E PowerQUICC II Pro Family integrates the enhanced e300 core and advanced features, such as DDR memory, Dual Gigabit Ethernet, Dual PCI and Hi-Speed USB controllers. With clock speeds scaling to 667 MHz, the MPC8349E family of processors offers the highest performing PowerQUICC II devices available.
The MPC8349E PowerQUICC II Pro Family is designed to provide a cost-effective, highly integrated control processing solution that addresses the emerging needs of networking, communications and pervasive computing applications. MPC8349E processors can be used in applications such as Ethernet routers and switches, wireless LAN (WLAN) equipment, network storage, home network appliances, industrial control equipment, and copiers, printers and other imaging systems.
e300 SoC Platform
The MPC8349E PowerQUICC II Pro Family is based on the e300 SoC platform—making it easy and fast to add or remove functional blocks and develop additional SoC-based family members targeting emerging market requirements. At the heart of the e300 SoC platform is Freescale Semiconductors e300 core. Based on the classic instruction-set architecture, the e300 core is an enhanced version of the 603e core used in previous-generation PowerQUICC II processors. Enhancements include twice as much L1 cache (32 KB data cache and 32 KB instruction cache) with integrated parity checking, and other performance-enhancing features. The e300 core is completely software-compatible with existing 603e core-based products.
Integrated Security
The MPC8349E Family features a powerful integrated security engine derived from Freescale Semiconductors security coprocessor product line. The MPC8349E Familys security engine supports DES, 3DES, MD-5, SHA-1, AES, and ARC-4 encryption algorithms, as well as a public key accelerator and an on-chip random number generator. The security engine is capable of single-pass encryption and authentication, as required by IPsec, IEEE® 802.11i standard and other security protocols.
图1. MPC8349EA方框图
MPC8349EA主要特性：
Major features of the MPC8349EA are as follows:
Embedded PowerPC e300 processor core; operates at up to 667 MHz
High-performance, superscalar processor core
Floating-point, integer, load/store, system register, and branch processing units
32-Kbyte instruction cache, 32-Kbyte data cache
Lockable portion of L1 cache
Dynamic power management
Software-compatible with the other Freescale processor families that implement Power Architecture technology
Double data rate, DDR1/DDR2 SDRAM memory controller
Programmable timing supporting DDR1 and DDR2 SDRAM
32- or 64-bit data interface, up to 400 MHz data rate
Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
Full error checking and correction (ECC) support
Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
Contiguous or discontiguous memory mapping
Read-modify-write support
Sleep-mode support for SDRAM self refresh
Auto refresh
On-the-fly power management using CKE
Registered DIMM support
2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
Dual controllers designed to comply with IEEE 802.3®, 802.3u®, 820.3x®, 802.3z®,
802.3ac® standards
Ethernet physical interfaces:
1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
Buffer deSCRJPTors are backward-compatible with MPC8260 and MPC860T 10/100
programming models
9.6-Kbyte jumbo frame support
RMON statistics support
Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
MII management interface for control and status
Programmable CRC generation and checking
Dual PCI interfaces
Designed to comply with PCI Specification Revision 2.3
Data bus width options:
Dual 32-bit data PCI interfaces operating at up to 66 MHz
Single 64-bit data PCI interface operating at up to 66 MHz
PCI 3.3-V compatible
PCI host bridge capabilities on both interfaces
PCI agent mode on PCI1 interface
PCI-to-memory and memory-to-PCI streaming
Memory prefetching of PCI read accesses and support for delayed read transactions
Posting of processor-to-PCI and PCI-to-memory writes
On-chip arbitration supporting five masters on PCI1, three masters on PCI2
Accesses to all PCI address spaces
Parity supported
Selectable hardware-enforced coherency
Address translation units for address mapping between host and peripheral
Dual address cycle for target
Internal configuration registers accessible from PCI
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs):
Public key execution unit (PKEU) :
RSA and Diffie-Hellman algorithms
Programmable field size up to 2048 bits
Elliptic curve cryptography
F2m and F(p) modes
Programmable field size up to 511 bits
Data encryption standard (DES) execution unit (DEU)
DES and 3DES algorithms
Two key (K1, K2) or three key (K1, K2, K3) for 3DES
ECB and CBC modes for both DES and 3DES
Advanced encryption standard unit (AESU)
Implements the Rijndael symmetric-key cipher
Key lengths of 128, 192, and 256 bits
ECB, CBC, CCM, and counter (CTR) modes
XOR parity generation accelerator for RAID applications
ARC four execution unit (AFEU)
Stream cipher compatible with the RC4 algorithm
40- to 128-bit programmable key
Message digest execution unit (MDEU)
SHA with 160-, 224-, or 256-bit message digest
MD5 with 128-bit message digest
HMAC with either algorithm
Random number generator (RNG)
Four crypto-channels, each supporting multi-command deSCRJPTor chains
Static and/or dynamic assignment of crypto-execution units through an integrated controller
Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
Universal serial bus (USB) dual role controller
USB on-the-go mode with both device and host functionality
Complies with USB specification Rev. 2.0
Can operate as a stand-alone USB device
One upstream facing port
Six programmable USB endpoints
Can operate as a stand-alone USB host controller
USB root hub with one downstream-facing port
Enhanced host controller interface (EHCI) compatible
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