摘要：多种原因会促使我们把以前使用高速微控制器(DS80C310/DS80C320/DS80C323/DS8xC520)的8051设计升级到新的超高速闪存微控制器(DS89C430/DS89C450)。促使产品升级的原因是：更高的性能、增值服务和外设以及灵活的内部闪存存储器。本应用笔记讨论了两个微控制器系列的重要差异，说明如何从高速升级到超高速器件。
概述
Maxim的高速微控制器系列包括多种不同的8051微控制器，与早期的8051每机器周期12个时钟相比，它们可以达到每机器周期4个时钟的更高速度。有些高速微控制器完全利用外部程序存储器，比如DS80C310；有些控制器包含内部EPROM或ROM程序存储器，比如DS87C520/DS83C520。这些高速器件都与现有的8051微控制器引脚兼容，所以在大部分情况下，更换一个快速器件并做很少的软件调整，就可以很容易升级设计。
通过同样的方式，超高速闪存微控制器可以替换高速微控制器设计进行升级。这些功能更强大的新型微控制器包括DS89C430/DS89C450，重要改进包括：扩展了内部程序闪存存储器(达到64kB)，重新设计的超高速微控制器核工作在单时钟周期指令，速度是早期8051设计的12倍。
本应用笔记讨论如何从高速微控制器升级到超高速闪存器件，介绍在升级设计时必须考虑的函数集、引脚的变动以及SFR的差异。
通用参考文献
下列器件的编程指南可以参考高速微控制器用户指南(PDF，English only)。
- DS80C310高速微控制器
- DS80C320高速低功耗微控制器
- DS80C323高速低功耗微控制器
- DS83C520高速ROM微控制器
- DS87C520高速EPROM微控制器
下列器件的编程指南请参考超高速闪存微控制器用户指南(PDF，English only)。
- DS89C430超高速闪存微控制器
- DS89C450超高速闪存微控制器
器件的基本功能
表1. 器件功能比较 FeatureDS80C310DS80C320
DS80C323DS87C520
DS83C520DS89C430
DS89C450Clocks per Machine Cycle4441Operating Voltage Range (V)4.5 to 5.54.25 to 5.5 (DS80C320)
2.7 to 5.5 (DS80C323)4.5 to 5.54.5 to 5.5Clock Rate (MHz, max)3333 (DS80C320)
18 (DS80C323)3333Instruction Execution Time (ns, min)121121 (DS80C320)
222 (DS80C323)12130Crystal Multiplier √ (x2 or x4)Ring Oscillator √√√Internal Program MemoryNoneNone16kB16kB (DS89C430)
64kB (DS89C450)Internal Register Memory (Bytes)256256256256Internal MOVX MemoryNoneNone1kB1kBSerial Ports (UARTs)1222External Interrupts6666Port Pins (with Bus Active)16161616Port Pins (max)16163232Timer/CountersThree/16-bitThree/16-bitThree/16-bitThree/16-bitWatchdog √√√Dual Data Pointers√√√√Autoincrement/Decrement √Stop Mode√√√√Power-On Reset√√√√Power-Fail Interrupt √√√
器件引脚排列
表2. 器件引脚的差异 DIPPLCCTQFPDS80C310DS80C320
DS80C323DS87C520
DS83C520DS89C430
DS89C4501240P1.0 (T2)P1.0 (T2)P1.0 (T2)P1.0 (T2)2341P1.1 (T2EX)P1.1 (T2EX)P1.1 (T2EX)P1.1 (T2EX)3442P1.2P1.2 (RXD1)P1.2 (RXD1)P1.2 (RXD1)4543P1.3P1.3 (TXD1)P1.3 (TXD1)P1.3 (TXD1)5644P1.4 (INT2)P1.4 (INT2)P1.4 (INT2)P1.4 (INT2)671P1.5 (nINT3)P1.5 (nINT3)P1.5 (nINT3)P1.5 (nINT3)782P1.6 (INT4)P1.6 (INT4)P1.6 (INT4)P1.6 (INT4)893P1.7 (nINT5)P1.7 (nINT5)P1.7 (nINT5)P1.7 (nINT5)9104RSTRSTRSTRST10115P3.0 (RXD0)P3.0 (RXD0)P3.0 (RXD0)P3.0 (RXD0)11137P3.1 (TXD0)P3.1 (TXD0)P3.1 (TXD0)P3.1 (TXD0)12148P3.2 (nINT0)P3.2 (nINT0)P3.2 (nINT0)P3.2 (nINT0)13159P3.3 (nINT1)P3.3 (nINT1)P3.3 (nINT1)P3.3 (nINT1)141610P3.4 (T0)P3.4 (T0)P3.4 (T0)P3.4 (T0)151711P3.5 (T1)P3.5 (T1)P3.5 (T1)P3.5 (T1)161812P3.6 (nWR)P3.6 (nWR)P3.6 (nWR)P3.6 (nWR)171913P3.7 (nRD)P3.7 (nRD)P3.7 (nRD)P3.7 (nRD)182014XTAL2XTAL2XTAL2XTAL2192115XTAL1XTAL1XTAL1XTAL12022, 2316, 17GNDGNDGNDGND–139GNDN/C (can be connected to GND if desired)GNDGND212418A8 (P2.0)A8 (P2.0)A8 (P2.0)A8 (P2.0)222519A9 (P2.1)A9 (P2.1)A9 (P2.1)A9 (P2.1)232620A10 (P2.2)A10 (P2.2)A10 (P2.2)A10 (P2.2)242721A11 (P2.3)A11 (P2.3)A11 (P2.3)A11 (P2.3)252822A12 (P2.4)A12 (P2.4)A12 (P2.4)A12 (P2.4)262923A13 (P2.5)A13 (P2.5)A13 (P2.5)A13 (P2.5)273024A14 (P2.6)A14 (P2.6)A14 (P2.6)A14 (P2.6)283125A15 (P2.7)A15 (P2.7)A15 (P2.7)A15 (P2.7)293226nPSENnPSENnPSENnPSEN303327ALEALEALEALE/nPROG313529nEAnEAnEAnEA323630AD7AD7AD7 (P0.7)AD7 (P0.7)333731AD6AD6AD6 (P0.6)AD6 (P0.6)343832AD5AD5AD5 (P0.5)AD5 (P0.5)353933AD4AD4AD4 (P0.4)AD4 (P0.4)364034AD3AD3AD3 (P0.3)AD3 (P0.3)374135AD2AD2AD2 (P0.2)AD2 (P0.2)384236AD1AD1AD1 (P0.1)AD1 (P0.1)394337AD0AD0AD0 (P0.0)AD0 (P0.0)404438VCC (+5V)VCC +5V (DS80C320)
VCC +3V (DS80C323)VCC (+5V)VCC (+5V)–126N/CN/CN/CVCC (+5V)–3428N/CN/CN/CGND
器件寄存器
表3. SFR映射比较 AddressDS80C310DS80C320
DS80C323DS87C520
DS83C520DS89C430
DS89C45080h––P0P081hSPSPSPSP82hDPLDPLDPLDPL83hDPHDPHDPHDPH84hDPL1DPL1DPL1DPL185hDPH1DPH1DPH1DPH186hDPSDPSDPSDPS87hPCONPCONPCONPCON88hTCONTCONTCONTCON89hTMODTMODTMODTMOD8AhTL0TL0TL0TL08BhTL1TL1TL1TL18ChTH0TH0TH0TH08DhTH1TH1TH1TH18EhCKCONCKCONCKCONCKCON90hP1P1P1P191hEXIFEXIFEXIFEXIF96h–––CKMOD98hSCONSCON0SCON0SCON099hSBUFSBUF0SBUF0SBUF09Dh–––ACONA0hP2P2P2P2A8hIEIEIEIEA9hSADDR0SADDR0SADDR0SADDR0AAh–SADDR1SADDR1SADDR1B0hP3P3P3P3B1h–––IP1B8hIPIPIPIP0B9hSADEN0SADEN0SADEN0SADEN0BAh–SADEN1SADEN1SADEN1C0h–SCON1SCON1SCON1C1h–SBUF1SBUF1SBUF1C2h––ROMSIZEROMSIZEC4h––PMRPMRC5hSTATUSSTATUSSTATUSSTATUSC7h–TATATAC8hT2CONT2CONT2CONT2CONC9hT2MODT2MODT2MODT2MODCAhRCAP2LRCAP2LRCAP2LRCAP2LCBhRCAP2HRCAP2HRCAP2HRCAP2HCChTL2TL2TL2TL2CDhTH2TH2TH2TH2D0hPSWPSWPSWPSWD5h–––FCNTLD6h–––FDATAD8hWDCONWDCONWDCONWDCONE0hACCACCACCACCE8hEIEEIEEIEEIEF0hBBBBF1h–––EIP1F8hEIPEIPEIPEIP0
表4. SFR功能区别 SFRBit(s)DifferencesP0–DS8xC520/DS89C430/DS89C450 only; controls Port 0 pins.DPS4 (AID)DS89C430/DS89C450 only; controls the autoincrement/decrement function for the active data pointer.5 (TSL)DS89C430/DS89C450 only; enables automatic toggling between data pointers after certain opcodes.6 (ID0)DS89C430/DS89C450 only; controls the effect of INC DPTR (increment or decrement) on DPTR.7 (ID1)DS89C430/DS89C450 only; controls the effect of INC DPTR (increment or decrement) on DPTR1.PCON4 (OFDE)DS89C430/DS89C450 only; crystal oscillator fail detection enable.5 (OFDF)DS89C430/DS89C450 only; crystal oscillator fail detection flag.CKCON7 (WD1)
6 (WD0)On all devices except the DS80C310; these bits control the watchdog timer period.EXIF0 (BGS)On all devices except the DS80C310; this bit enables/disables the bandgap reference during stop mode.1 (RGSL)On all devices except the DS80C310; this bit controls execution from the ring oscillator during the crystal warmup period.2 (RGMD)On all devices except the DS80C310; this flag indicates the current clock source (ring or crystal).3DS8xC520 (XT/nRG); selects the ring oscillator or crystal as the desired clock source.
DS89C430/DS89C450 (CKRY); indicates that the crystal oscillator or crystal multiplier has completed its warmup period.CKMOD3 (T0MH)DS89C430/DS89C450 only; allows Timer 0 to run directly from the system clock (clock/1).4 (T1MH)DS89C430/DS89C450 only; allows Timer 1 to run directly from the system clock (clock/1).5 (T2MH)DS89C430/DS89C450 only; allows Timer 2 to run directly from the system clock (clock/1).ACON5 (PAGES0)
6 (PAGES1)DS89C430/DS89C450 only; selects the page-mode configuration for external bus operations.7 (PAGEE)DS89C430/DS89C450 only; enables page mode (as opposed to the standard 8051 expanded bus mode) for external bus operations.IE6 (ES1)On all devices except the DS80C310; this bit enables/disables the serial port 1 interrupt.SADDR1–On all devices except the DS80C310; this register controls the slave address for serial port 1.IP1–DS89C430/DS89C450 only; this register combines with the settings in IP0/IP to provide four priority-level settings for each interrupt (as opposed to two settings with IP only).SADEN1–On all devices except the DS80C310; this register sets the slave address mask for serial port 1.SCON1–On all devices except the DS80C310; this register controls mode settings for serial port 1.SBUF1–On all devices except the DS80C310; this register provides the input/output buffer for serial port 1.ROMSIZE2:0 (RMS2:0)DS8xC520/DS89C430/DS89C450 only; selects the range of on-chip EPROM/flash that maps into program space.3 (PRAME)DS89C430/DS89C450 only; enables/disables mapping of the 1kB internal RAM into program space.PMR1:0 (DME1:0)DS8xC520/DS89C430/DS89C450 only; controls mapping of internal data memory into data space.2DS8xC520 (ALEOFF); when set to 1, disables ALE during on-board memory access.
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本文关键字：控制器系列 电工文摘，电工技术 - 电工文摘
