最初为控制模型火车而设计， 积分器斜向上或下，以预设比率响应输入直流水平的改变，并保持电路输入电压水平。
运放积分器可以斜上升到饱和状态，电容放电式开关会重置积分器。或者，三角波发生器应用中，输入转换积分器，使其冲高或跌落。通过在线常用电路的许多研究发现运放积分器保持预设持续电压是没有意义的。本设计方案描述了一个单电源供电放大器电路，电路输出斜坡上升或下降的线性电压，响应0到VCC正直流输入电压的阶梯改变。如图1中数值，输出斜坡的dV/dt可调整到1V/minut，不依赖于输入阶梯的幅值，终止于与输入阶梯电压近似相等的恒定直流等级。任何更多直流输入电压的改变引起以预设dV/dt速度，输出斜坡上升或下降到新直流输入电压。实际上，电路是一个限幅的恒定斜率积分器。
电路使用NI公司轨对轨输入/输出四运放LMC6484。轨对轨的特性使其容易使用，低漏输入适用于长期不变得积分器，最大3mV输入偏置电压更是出色。线性锥形电位器R1设置输入电压，从而在斜坡末端决定最后输出电压。当输出斜坡上升或下降时，IC1A的输出分别在VCC或地饱和。
无极性电容C1和线性锥形电位器R2决
定积分器IC1B的时间常数。调整域为0.5V/msec到1V/minute。IC1B的参考偏置为108 mV，其来源于为分隔R7和R8的单倍增益缓冲器IC1D。切断电源时，R6确保不会超过IC1B的输入电流，C1通过IC1B的输入和输出二极管放电，R2最小值时，IC1B的输出不会过分负载回IC1D的输出。
R3和R4隔开饱和的IC1A输出到几乎100 mV，无负载情况下为108mV左右偏置。这个分隔引发R5上压降几乎为20 mV，以积分器C1和R2设置的速率向上或向下回转IC1B；运放可能的3mV输入偏置电压加上最小化偏置效果，20 mV是合适的。当IC1B的输出电压斜坡达到R1插头的输入电压时，倘若循环负反馈维持积分器IC1B的输出与输入电压相等，IC1A脱离饱和，并重置到几乎2.5V。这个动作设置积分器斜坡终端电压的界限。对驱动发动机电路（没有显示），IC1C可以不用，或像图片所示，用一个三角波信号驱动其转换IC1B的直流电压或斜坡到相应的 PWM （脉宽调制）信号。
R5消除偏压电阻器公差产生的微分误差，它提供了25°C下Ic1B的3V最大输入偏置电压和允许最慢dV/dt的20mV输入幅值的折衷。图中值导致几乎1V/minute的最大时间或5minutes全速达到5V VCC。如果需要更长时间可以提高VCC到15V，用调整偏置电阻或通过使用并联无极性电容增加C1值的方式。或者，虽然电位器大于1 MΩ值的选择很少，但还是可以增加R2的值来实现。
如果应用不需要长时间常数或如果使用上述方法增加时间常数，可以用IC1B更高差分输入的代价消除R5，相对的积分更快。也可以消除IC1D和直接连接IC1B管脚5的R7、R8电阻偏置分隔器，但是为使微分误差最小，电阻误差会变得更严格（参考文献1、2）。
英文原文：
Integrator ramps up/down, holds output level
Originally designed for controlling a model train, the integrator ramps up or down at a preset rate in response to changes in the input-dc level and holds at the circuit's input voltage level.
Glen Chenier, TeeterTotterTreeStuff, Allen, TX; Edited by Charles H Small and Fran Granville -- EDN, 9/27/2007
Op-amp integrators CAN ramp to saturation, and a caPACitor-discharge switch can reset them. ALTErnatively, you can input-switch them to ramp up and down in triangle-waveform-generator applications. Much searching through online “cookbook” circuits turned up no means of ramPINg an op-amp integrator to hold at a preset constant voltage level. This Design Idea describes a single-supply op-amp circuit that outputs a rising or falling linear-voltage ramp in response to a step change of a positive dc-input voltage of 0V to VCC. The output ramp’s dV/dt slope is adjustable to 1V/minute with the values in Figure 1, is independent of the input-step amplitude, and terminates at a constant dc level approximately equal to the input-step voltage. Any further change in the dc-input voltage causes the output to ramp up or down at the preset dV/dt to the new dc-input voltage. In effect, this circuit is an amplitude-bounded constant-slope integrator.
The circuit uses a rail-to-rail I/O quad op amp, the National SEMIconductor LMC6484. The rail-to-rail feature makes it easy to use, the low input leakage is great for long-time-constant integration, and the 3-mV maximum input-offset voltage is respectable. Potentiometer R1, a linear taper, sets the input voltage for final output voltage after the ramp ends. IC1A’s output is in saturation at VCC or ground while the output is ramPINg down or up, respectively.
Nonpolarized caPACitor C1 and potentiometer R2, a linear taper, determine the time constant of integrator IC1B. The adjustment range is 0.5V/msec to 1V/minute. The reference bias for IC1B is 108 mV, which you derive from IC1D as a unity-gain buffer for divider R7 and R8. R6 ensures that you do not exceed IC1B’s input current when you turn off the power, that C1 discharges through IC1B’s input and output diodes, and that IC1B’s output does not excessively load back into IC1D’s output with R2 at a minimum.
R3 and R4 divide the saturated IC1A’s output to approximately 100 mV unloaded above or below the 108-mV bias. This division causes approximately 20 mV to drop across R5 to slew IC1B upward or downward at the integration rate that C1 and R2 set; 20 mV is comfortably above the op amp’s possible 3-mV input-offset voltage to minimize offset effects. When IC1B’s output-voltage ramp reaches that of the input voltage from the R1 wiper, IC1A comes out of saturation and rests at approximately 2.5V, providing the loop-negative feedback to maintain integrator IC1B’s output equal to the input voltage. This action sets the boundary on the integration ramp’s terminal voltage. IC1C CAN be spare, or, as the figure shows, you can drive it with a triangle-wave signal to convert IC1B’s dc level or ramp to a corresponding PWM (pulse-width-modulated) signal for a motor-drive circuit (not shown).
R5 eliminates differential errors arising fro m bias-resistor tolerance, and it provides a compromise between IC1B’s 3V maximum input-offset voltage at 25°C and 20-mV input amplitude to allow the slowest dV/dt. The values in the figure result in a maximum time of approximately 1V/minute, or 5 minutes at VCC of 5V to reach full speed. If you require longer times, you can raise VCC to 15V with adjustments to the bias resistors or raise C1’s value by using parallel nonpolarized capacitors. ALTErnatively, you could raise R2’s value, although selection is sparser for potentiometers with values greater than 1 MΩ.
If your application does not require a long time constant or if you use the aforementioned methods to increase the time constant, you can eliminate R5 at the expense of a higher level differential input to IC1B and correspondingly faster integration. You could also eliminate IC1D and the R7-R8 resistive-bias divider that connects directly to IC1B’s Pin 5, but resistor tolerance becomes more critical to minimize differential error (reference 1 and reference 2).
References
1 “Tractive effort, acceleration, and braking,” The Mathematical Association, 2004.
2 Woof, Tony, “Kilo newtons, kilo watts, kilometres per hour,” 2001.
英文原文地址： http://www.edn.com/article/CA6479492.html
本文关键字：暂无联系方式运算放大器，单元电路 - 运算放大器
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