NS公司的LMH1982是多速率视频时钟发生器，能同时产生SD和HD时钟与一个Top of Frame（TOF）脉冲，广泛应用在3-Gbps (3G)，高清（HD)和标清（SD）视频应用如视频同步，串行数字接口（SDI）SERDES，视频转换，视频编辑和其它广播和专业视频系统。本文介绍了LMH1982的主要性能，方框图以及典型的系统方框图，并介绍了用于三速SDI视频的多种参考时钟电路。
LMH1982 Multi-Rate Video Clock Generator with Genlock
The LMH1982 is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.
The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the devices phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Nationals LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.
The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz
VCXO and loop filter are externally required for gunlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize
jitter transfer. HD clock output jitter as low as 40 ps peak-topeak can help designers using FPGA serializers meet stringent SDI output jitter specifications.
The LMH1982 is offered in a space-saving 5 mm x 5 mm 32- pin LLP package and provides low total power dissipation of 250 mW (typical).
主要特性：
■ Two simultaneous LVDS output clocks with selectable frequencies and Hi-Z capability:
—SD clock: 27 MHz or 67.5 MHz
—HD clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or 148.5/1.001 MHz
■Low-jitter output clocks may be directly connected to an FPGA serializer to meet SMPTE SDI jitter specifications
■Top of Frame (TOF) pulse with programmable output format timing and Hi-Z capability
■Two reference ports (A and B) with H and V sync inputs
■Supports cross-locking of input and output timing
■External loop filter allows control of loop bandwidth, jitter transfer, and lock time characteristics
■Free run or Holdover operation on loss of reference
■User-defined free run control voltage input
■I2C interface and control registers
■3.3V and 2.5V supplies
应用：
■Video genlock and synchronization
■Triple rate 3G/HD/SD-SDI SerDes
■Video capture, conversion, editing and distribution
■Video displays and projectors
■Broadcast and professional video equipment
图1.典型的系统方框图
图2. LMH1982方框图
图3.用于三速SDI视频的模拟参考时钟Genlock
图4.用于三速SDI视频的SDI参考时钟Genlock
图5.三速SDI环通 (loop-through)
图6.用于三速SDI视频的组合Genlock或环通 (loop-through)
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