Phase-lock loop (PLL) for versatile clock-in scheme and sensitivity
指标:
Imaging Array
Optical Format: 1/2.5-inch
Active Array: 2592(H) x 1944(V)
Imaging Area: 5.70mm(H) x 4.28mm(V)
Speed/Output
Frame Rate: 15 fps at full resolution 30 fps at 1080p resolution (1920H x 1080V)
Up to 60 fps at 720p resolution
Data Rate: 96 Mp/s
Master Clock: 96 MHz
Data Format: 12-bit parallel Sensitivity
Pixel Size: 2.2μm x 2.2μm
Dynamic Range: 70.1dB (full resolution) 76dB (2 x 2 binning)
Responsivity: 1.4 V/lux-sec (550nm) Power
Supply: Analog: 2.6–3.1V (2.8V nominal)
Digital: 1.7–1.9V (1.8V nominal)
I/O: 1.8–3.1V
Consumption: <260mW
Temperature Range
Operating: –30°C to +70°C
Package: 48-pin iLCC or Die
图3. MT9P031方框图上一页 [1] [2]
本文关键字：网络 电子技术，电工技术 - 电子技术
